Existing chip design process flow may be summarized as follows. 1) A chip designer typically starts with an intended design for a chip. 2) A reticle simulator program may be used to convert the intended design to a reticle layout, which may be stored as a design file. 3) A reticle is manufactured using the reticle layout. 4) The reticle may then be used to print a pattern on a substrate such as a semiconductor wafer. 5) The printed pattern may then be compared to the intended design. If the comparison shows that the printed pattern is sufficiently close to the intended design, the reticle may be used for production. If the printed pattern is not sufficiently close to the intended design, the reticle simulator program may use differences between the printed pattern and the intended design to modify the reticle layout. Steps 2), 3) 4) and 5) may be repeated iteratively until the printed pattern is sufficiently close to the intended design.
This process flow may be first performed on a test structure and on a variety of substrate films, and with a variety of stepper illumination configurations. The results of the work done on the test structures may be compared to simulation results in order to tune the simulator for a particular technology and yield designs that are right the first time. However, simulators often do not accurately predict what gets printed when a reticle is put into service.
There are a number of potential sources of error in the process of calibrating a reticle simulator. Such sources may include insufficient accuracy in the stepper parameters, resist parameters and reticle dimensions.
It is within this context that embodiments of the present invention arise.